Electronic devices such as computer peripherals, digital cameras, hand held communications and data tools typically include application-specific integrated circuits (ASIC). These ASIC chips are custom designed to satisfy the needs of the product without excess features or capabilities that would needlessly increase the component cost. While a fully custom ASIC provides a cost effective solution for many products, the need for a custom design may limit ASIC usage to higher volume products where the cost of a custom design may be economically amortized. In addition, the duration of the design phase may make the ASIC alternative less attractive than a higher-cost off the shelf IC that can fulfill market demand more immediately.
The design cost and lead time disadvantages may be largely ameliorated by the usage of standard functional modules that are essentially the building blocks of an ASIC. These include central processing units (CPU), interface modules, and memory modules. Instead of designing the entire circuit from scratch, the ASIC designer selects an appropriate collection of off-the-shelf modules, customizes them only as needed, and interconnects them appropriately. The application specific data or instruction sets, or interface circuitry may be included on the ASIC as part of the custom design. In general, it is desirable to minimize the amount of custom work required for a new ASIC.
One ASIC feature that may vary widely from product to product is memory module size. To operate efficiently, the CPU on the chip may have associated memory, such as read only memory (ROM) or random access memory (RAM), or both. To ensure that the memory contents are correct, or that the memory is properly writable and or readable, a memory test capability is normally required. While an unpackaged chip may be probed with contacts from an external tester to exercise the memory, this is unsuitable for testing that may occur each time that the product is operated by the user, and may be unduly slow. Access by the tester to on-chip memory may also be practically limited due to the high cost of pin access, as increasing the number of dedicated test pins increases package size and cost.
To provide faster and more versatile memory testing without external hardware, built-in self testing (BIST) modules have been developed to reside on the ASIC, with a BIST module associated with each memory module. Each BIST module is custom designed for the size of the memory, and operates to send address information to the memory, and read out the data from each address to compare with expected results (RAM testers may also write data to the memory). The BIST must address and read all memory addresses, and stop when all addresses have been read. Proceeding beyond the proper addresses may cause the rereading of the initial addresses or other errors, corrupting test results. There are numerous well known testing algorithms that allow rapid and efficient memory testing.
For memory attached directly to the CPU, it is preferable to include the BIST modules as part of a standard CPU because the design tools used for the semi-custom design process are better able to optimize the timing and circuit layout by designing the CPU and BIST together. With the BIST in the CPU, this advantage may be achieved, but at the cost of requiring the BIST portions of the CPU to be redesigned for each new permutation of memory sizes, with the disadvantages noted above.
The present invention overcomes the limitations of the prior art by providing an ASIC with a CPU module and a memory module connected to the CPU. The memory has a size selected from a set of alternative memory sizes. The CPU has a memory interface device with an output connected to the memory, and includes a memory test device connected to the memory. The memory test device has a size selector input that receives a memory size code, so that the memory test device is operable to test a memory module of any of the alternative memory sizes in response to alternative memory size codes received on the size selector input. The memory may be RAM or ROM, and the size codes may correspond to address size data and or data size data stored in the memory test device.